1. Field
Embodiments described herein relate generally to a semiconductor integrated circuit.
2. Background Art
In a conventional method of detecting failures in a manufacturing test, a built-in self-test (BIST) circuit is incorporated into a memory device mounted in a semiconductor integrated circuit.
Such failure detection methods include a comparator-type BIST in which written data and read data are compared to each other to decide the presence or absence of failures and a compressor-type BIST in which read results are compressed in a BIST circuit to decide the presence or absence of failures based on compression results.
Generally, multiple BIST circuits are mounted on a semiconductor integrated circuit and each of the BIST circuits conducts a test on multiple memories. When the multiple memories are tested by a single BIST circuit during testing, the memories are tested in parallel or one by one.
In a configuration for testing all memories in parallel, unfortunately, an additional analysis circuit needs to be provided on each of the outputs of the memories, which leads to a larger circuit size.
In a configuration for testing memories one by one, the memories cannot be all simultaneously tested. Thus, the total testing time is the sum of the testing times of the target memories.
Therefore, these configurations are disadvantageous for LSI manufacturing and testing.